Mod-N Counter: Non-50% Duty Cycle Analysis
A synchronous mod-5 counter increments its internal binary state from 0 to 4 on every positive edge of the clock, returning to 0 after reaching 4 or when the synchronous reset is active. Three signals are shown: CLK (clock, period 2), RST (synchronous active-high reset), and Q0 (the least significant bit of the internal state, initially 0). Trace Q0 across all 16 time steps to observe its non-50% duty cycle.
Constraints
- The counter state updates only on the LOW-to-HIGH transition of
CLK. - The internal state uses standard binary encoding: 000, 001, 010, 011, 100.
RSTis synchronous and takes priority over the counting action.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.