Mod-60 Counter
Digital clocks, timers, and stopwatches rely on cascaded modulus counters to track time accurately. The seconds tracking module requires a multi-stage counter that loops continuously from 00 to 59.
The circuit must implement a Mod-60 counter using two cascaded stages: a ones digit (ones) and a tens digit (tens). The ones output must increment every clock cycle to count from 0 to 9. When ones equals 9, it must generate a terminal count signal that enables the tens stage to increment on the following clock cycle. The tens output must count from 0 to 5. At the maximum count of 59 (where tens equals 5 and ones equals 9), both stages must roll over to 0 on the next clock edge. An asynchronous reset rst must clear both digits to 0 immediately when asserted high.
Constraints
- Output exactly 4 bits for
onesand 3 bits fortens. - Use cascaded sequential logic components to separate the two digit stages.
- Derive the increment enable signal for the
tensstage strictly from the terminal count of theonesstage. - Do not build a single 6-bit binary counter and apply mathematical division to extract digits.
Topics
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