Programmable Modulus Counter: Comparator-Based Reset
Frequency synthesizers, hardware timers, and test equipment require dividers that can change their modulus at runtime. A programmable modulus counter achieves this by comparing its current state against a target value provided by a control bus.
The circuit receives a clock clk, a synchronous reset rst, and a 3-bit target value PROG[2:0]. It outputs the current 3-bit count Q[2:0]. The counter increments by 1 on each rising edge of clk. A 3-bit equality comparator continuously checks if Q[2:0] equals PROG[2:0]. When a match occurs, the comparator output must force the counter to synchronously reset to 0 on the next clock edge. A high rst signal also forces Q[2:0] to 0 on the next clock edge.
| rst | Q == PROG | Next Q | |-------|-------------|----------| | 1 | X | 0 | | 0 | 1 | 0 | | 0 | 0 | Q + 1 |
For example, if PROG[2:0] is set to 3 (binary 011), the counter sequence will be 0, 1, 2, 3, 0, 1, 2, 3.
Constraints
- Implement the counter state using D flip-flops.
- Build the 3-bit equality comparator explicitly using XNOR and AND gates.
- The reset triggered by the comparator must be fully synchronous.
Topics
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