Modport Direction Enforcement
SystemVerilog interfaces bundle related signals together to simplify module connections.
Expected behavior:
| m_in | s_in | m_ready | s_valid | |--------|--------|-----------|-----------| | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 |
The interface connects a master and a slave. The master module drives m_ready based on m_in, and the slave module drives s_valid based on s_in.
Simulation shows m_ready = X for input m_in=1, s_in=1. The ready signal is corrupted by a multiple-driver conflict. Inspect the design and correct the fault. Use modports to enforce strict port directions and prevent illegal assignments.
Constraints
- Apply SystemVerilog
modportdeclarations to the interface. - Update the module ports to use the defined modports to enforce signal directions at compile time.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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