Multiple Nonblocking Assignments
Hardware synthesis tools rely on strict evaluation rules to translate procedural blocks into predictable sequential logic.
The RTL snippet below defines a clocked process driving a register q.
always @(posedge clk) begin
q <= d;
if (en) begin
q <= 1'b0;
end
endMultiple nonblocking assignments target q within the same cycle. This includes a default assignment and a conditional override based on the signal en.
Determine the resulting synthesized logic and the simulated behavior of q for various input conditions.
Constraints
- Assume standard Verilog execution semantics.
clk,d, andenare synchronous 1-bit inputs.qis a 1-bit register.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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