One Hot Enum Encoding Verification
High-speed state machines rely on one-hot encoding to minimize combinational logic depth and meet aggressive timing closures. The provided SystemVerilog snippet defines a state machine using an enumerated type for its states: IDLE, READ, WRITE, and DONE. The enum base type and explicit literal values are configured to force a one-hot representation. The synthesized netlist maps this enum to a state register state_q and next-state logic state_d.
Analyze the enum declaration and the resulting synthesis netlist. Determine the required bit width for the state register and identify how the synthesis tool allocates flip-flops for the state vector.
Constraints
- The enum must explicitly define a base type width that matches the number of states.
- The synthesis tool must preserve the exact register count without optimizing away unused encodings.
Topics
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