ROM Based State Machine Next State Logic
Microcode sequencers in complex CPUs often replace dense combinational control paths with lookup tables. A ROM-based finite state machine uses the current state and external inputs as an address to fetch the next state directly from memory.
Implement a 2-bit saturating counter using a ROM array for the next-state logic. The counter increments when en is 1 and holds its value when en is 0. The maximum value is 3. The ROM address lines must be driven by the current state bits S1 and S0, along with the enable signal en. The ROM data outputs must drive the next state bits N1 and N0.
| S1 | S0 | en | N1 | N0 | |------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 0 | 1 | | 0 | 1 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 1 | 1 |
Constraints
- Use a ROM component for all next-state combinational logic.
- Do not use discrete logic gates for the next-state calculation.
- Use D flip-flops for the state register.
- Connect
rstdirectly to the asynchronous reset pins of the flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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