Overflow Ignored in Accumulator
A 16-bit accumulator adder computes the sum of the current accumulator value A and the new operand B. It must assert the Ovf flag when the signed 16-bit addition exceeds the valid two's complement range.
Expected behavior:
The Sum output provides the lower 16 bits of the addition. The Ovf output is 1 if both inputs are positive and the result is negative, or if both inputs are negative and the result is positive. Otherwise, Ovf is 0.
Simulation shows Ovf = 0 for inputs A = 20000 and B = 20000. The output Sum correctly evaluates to 40000 (which represents -25536 in two's complement), but the overflow flag fails to assert. This causes the DSP pipeline to silently drop massive values. Inspect the circuit and correct the fault.
Constraints
- The circuit must correctly compute the 16-bit sum of
AandB. - The
Ovfflag must be driven high only during a signed overflow condition. - Inputs and outputs are represented as 16-bit unsigned integers in the test vectors.
Topics
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