Pipeline Data Hazard
A pipelined processor datapath executes instructions in overlapping stages to increase throughput. The forwarding unit must detect Read-After-Write hazards and route the previous ALU result directly to the execution stage of the dependent instruction.
Expected behavior:
The forwarding control signal ForwardA must assert high (1) when the previous instruction writes to the register file (RegWrite_M = 1) and its destination register (WriteReg_M) matches the current instruction's source register (Rs_E).
Simulation shows ForwardA = 0 when RegWrite_M = 1, WriteReg_M = 2, and Rs_E = 2. The ALU computes with stale register data instead of the forwarded value. Inspect the circuit and correct the fault.
Constraints
- Do not add additional pipeline registers.
- Modify only the forwarding unit logic to resolve the hazard.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.