Pipeline Register Between Combinational Stages
A two-stage pipeline uses a positive-edge-triggered register to isolate two combinational addition stages. Stage 1 computes A XOR B and the pipeline register captures this intermediate result on every LOW-to-HIGH transition of CLK. Stage 2 computes the final output by evaluating the captured register value XORed with C.
Five signals are shown: CLK (clock, period 4), A (Stage 1 input), B (Stage 1 input), C (Stage 2 input), and OUT (Stage 2 output). The pipeline register initially holds 0.
Trace OUT across all 16 time steps.
Constraints
- The pipeline register only updates its stored value exactly at the LOW-to-HIGH clock transitions.
- Stage 2 is purely combinational:
OUTupdates immediately wheneverCchanges or when the pipeline register updates. - Mid-cycle changes to
AorBdo not affectOUTuntil the next rising clock edge.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.