PIPO: Register File Row Concept
Register files in processors and memory controllers rely on arrays of parallel-in parallel-out registers to store state. Write-enable gating ensures that data on a shared input bus is captured exclusively by the targeted row, preserving the state of all other rows.
Construct four independent 4-bit registers. Each register outputs to its respective 4-bit port: Q0, Q1, Q2, and Q3. All four registers share a single 4-bit input bus D and a common clock CLK. Each register is controlled by its own dedicated write-enable signal: WE0, WE1, WE2, and WE3.
On the rising edge of CLK, a register must capture the value of D if its corresponding WE signal is 1. If its WE signal is 0, the register must hold its current value.
| CLK | WEx | D (4-bit) | Qx (next state) | |-------|-------|-------------|-------------------| | ↑ | 0 | Data | Qx (current) | | ↑ | 1 | Data | D |
Constraints
- Implement four distinct 4-bit storage elements.
- Do not gate the clock signal to control writes.
- Use multiplexers or clock-enabled flip-flops to control data capture.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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