PIPO: Arithmetic Right Shift (Sign-Extended)
A 4-bit positive-edge-triggered arithmetic right shift register preserves the sign bit during a shift operation by feeding Q3 back into itself.
Eleven signals are shown: CLK (clock, period 2), LOAD (synchronous parallel load), SHIFT (synchronous right shift), four data inputs D3 through D0, and four register outputs Q3 through Q0 (initially all 0).
Trace outputs Q3, Q2, Q1, and Q0 across all 12 time steps.
Constraints
- On the rising edge of
CLK, ifLOADis 1, the register captures the values ofD3throughD0. - On the rising edge of
CLK, ifSHIFTis 1 andLOADis 0, the register shifts right arithmetically:Q2getsQ3,Q1getsQ2,Q0getsQ1, andQ3retains its previous value. - The outputs only change state strictly on the LOW-to-HIGH transition of
CLK.
Topics
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