PIPO: 8-Bit Register with Synchronous Clear Priority
Datapath elements require predictable initialization during system reset sequences. A parallel-in parallel-out (PIPO) register must guarantee that reset signals take absolute precedence over incoming data to prevent latching invalid states.
The 8-bit register captures the input D on every rising clock edge. The synchronous clear signal CLR acts as a strict override. When CLR is asserted, the register must load all zeros on the clock edge regardless of the value on D.
| CLR | D | Q (next state) | |-------|-----|------------------| | 1 | X | 0 | | 0 | Val | Val |
Constraints
- Update the output
Qonly on the rising edge of the clock. - Implement
CLRas a fully synchronous control signal. - Enforce strict priority for
CLRover the data inputD.
Topics
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