4-Bit Universal Shift Register: Four-Mode Design
Universal shift registers act as the primary data manipulation blocks in digital systems, handling serial-to-parallel conversion, parallel-to-serial conversion, and arithmetic bit-shifting within a single integrated component.
The circuit uses MODE1 and MODE0 to select the operation of four D flip-flops on the rising edge of clk. A 4-to-1 multiplexer at each flip-flop's input determines its next state. In this architecture, Q0 represents the leftmost bit and Q3 represents the rightmost bit.
| MODE1 | MODE0 | Operation | Q0 (Left) | Q1 | Q2 | Q3 (Right) | |---------|---------|-----------|-------------|------|------|--------------| | 0 | 0 | Hold | Q0 | Q1 | Q2 | Q3 | | 0 | 1 | Shift Right| SER_R | Q0 | Q1 | Q2 | | 1 | 0 | Shift Left| Q1 | Q2 | Q3 | SER_L | | 1 | 1 | Load | P0 | P1 | P2 | P3 |
Constraints
- Implement exactly four D flip-flops.
- Use a 4-to-1 multiplexer to drive the data input of each flip-flop.
- Update all flip-flop states synchronously on the rising edge of
clk.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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