PIPO: Load and Shift Priority When Both Asserted
A Parallel-In Parallel-Out (PIPO) register with shift capabilities stores data or shifts it based on control signals. The LOAD signal must take priority over the SHIFT signal when both are asserted simultaneously.
Expected behavior:
| LOAD | SHIFT | Action | |--------|---------|--------| | 0 | 0 | Hold state | | 0 | 1 | Shift SIN into Q3, shift rest right | | 1 | 0 | Load D[3:0] into Q[3:0] | | 1 | 1 | Load D[3:0] into Q[3:0] |
Simulation shows the register shifting data instead of capturing the parallel input when both control signals are asserted. For test case LOAD=1, SHIFT=1, SIN=0, and D=1111 starting from state Q=1010, the output updates to Q=0101 instead of the expected Q=1111. Inspect the circuit and correct the fault.
Constraints
- Modify only the control logic routing to the multiplexer select pins.
- Do not add or remove any D flip-flops.
Topics
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