PIPO: Shift-Left as Multiply by 2
A positive-edge-triggered 4-bit Parallel-In Parallel-Out (PIPO) shift register performs arithmetic left shifts to multiply values by 2. When LOAD is 1, the register captures parallel data inputs D3, D2, D1, and D0 on the LOW-to-HIGH transition of CLK. When SHIFT is 1 and LOAD is 0, the register shifts all bits left by one position on the rising clock edge: Q0 receives 0, and the previous Q3 shifts out into the overflow flag OVF. During a load operation, OVF is cleared to 0. Twelve signals are shown: CLK (clock, period 2), LOAD (control), SHIFT (control), four data inputs (D3, D2, D1, D0), four outputs (Q3, Q2, Q1, Q0, all initially 0), and OVF (overflow flag, initially 0). Trace the five output signals Q3, Q2, Q1, Q0, and OVF across all 12 time steps.
Constraints
LOADtakes priority overSHIFTif both are asserted simultaneously.- A left shift always introduces a 0 into the Least Significant Bit (
Q0).
Topics
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