PIPO with LOAD and SHIFT Capability
Universal shift registers form the backbone of serial-to-parallel converters, ALU data alignment circuits, and memory I/O interfaces. Adding a shift mode to a parallel-in parallel-out (PIPO) register allows data to be loaded in bulk and then streamed out serially or shifted for fast arithmetic operations.
The circuit requires a 4-bit register with two operating modes controlled by the mode signal. When mode is 0, the register captures the parallel inputs D3, D2, D1, and D0 on the rising edge of clk. When mode is 1, the register shifts its contents one position to the right per clock cycle. During a shift, shift_in feeds the most significant bit (Q3), and each subsequent bit receives the value of the bit to its left.
| mode | Q3 (next) | Q2 (next) | Q1 (next) | Q0 (next) | |--------|-------------|-------------|-------------|-------------| | 0 | D3 | D2 | D1 | D0 | | 1 | shift_in | Q3 | Q2 | Q1 |
Constraints
- Use exactly four D flip-flops for state storage.
- Use 2:1 multiplexers to route data to the D inputs based on the
modesignal. - All state updates must be strictly synchronous to the rising edge of
clk. - Do not use high-level shift register primitives.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.