4-Bit PIPO: One-Cycle Register Latency
A positive-edge-triggered 4-bit Parallel-In Parallel-Out (PIPO) register captures the values of D3, D2, D1, and D0 at every LOW-to-HIGH transition of CLK and holds them until the next rising edge.
Nine signals are shown: CLK (clock, period 2), D3, D2, D1, D0 (inputs), and Q3, Q2, Q1, Q0 (outputs, initially 0, 1, 0, 1 respectively).
Trace Q3, Q2, Q1, and Q0 across all 8 time steps.
Constraints
- The register is strictly positive-edge-triggered.
- Input changes that occur exactly on the clock edge are not captured until the next rising edge due to setup time requirements.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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