4-Bit PIPO Register: Basic Construction
Data paths inside microprocessors require intermediate storage to hold values between pipeline stages. The parallel-in, parallel-out (PIPO) register provides this fundamental buffering, capturing a multi-bit word on a clock edge and holding it steady for the downstream logic.
Construct a 4-bit PIPO register using individual D flip-flops. The circuit must capture the inputs D3, D2, D1, and D0 on the rising edge of CLK. The captured values must be driven to the respective outputs Q3, Q2, Q1, and Q0. The outputs must reflect the sampled inputs exactly one clock cycle later.
| CLK | D (Any Bit) | Q (Next State) | |-------|---------------|------------------| | 0 | X | Q (Current) | | 1 | X | Q (Current) | | ↑ | 0 | 0 | | ↑ | 1 | 1 |
Constraints
- Use exactly four D flip-flops.
- Connect the single global
CLKinput to every flip-flop clock pin. - Do not use any combinational logic gates.
- Do not connect any
Qoutput back to aDinput.
Topics
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