PISO vs. Multiplexer: Design Trade-off Analysis
Parallel-to-serial conversion dictates the fundamental trade-off between physical routing resources and transmission latency in system-on-chip design.
The scenario evaluates two methods for transmitting an 8-bit data payload between two hardware modules. Design A uses an 8-bit Parallel-In Serial-Out (PISO) shift register requiring 1 data output wire and 1 CLK wire. Design B uses a parallel multiplexer configuration requiring 8 data wires and 3 select wires to transmit the entire 8-bit word concurrently. Both systems operate at a continuous CLK frequency of 100 MHz.
Compare the cycle count, wire count, and data throughput of both designs to determine the optimal architecture for different physical constraints.
Constraints
- Throughput is defined as the total number of payload bits successfully transmitted per second.
- Wire count includes only the specific interconnects listed between the source and destination modules.
- Design A requires 8 full clock cycles to shift out the 8-bit payload.
- Design B requires 1 clock cycle to transmit the 8-bit payload.
Topics
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