PISO: Serial Output Timing Relative to Load Cycle Annotation
A 4-bit Parallel-In Serial-Out (PISO) shift register internally captures parallel data on the positive clock edge when LOAD is HIGH, and begins serial transmission on the following positive clock edge.
Six signals are shown: CLK (clock, period 2), LOAD (synchronous active-HIGH load enable), and D3 through D0 (4-bit parallel data input, where D3 is the MSB). The serial output SOUT is initially 0 and outputs 0 when not transmitting.
Trace SOUT across all 20 time steps.
Constraints
SOUTupdates only on the positive edge ofCLK.- The first transmitted bit is the MSB (
D3), appearing exactly one clock cycle after theLOADcapture edge. - The parallel data inputs
D3throughD0fluctuate: you must capture their exact values only during the specific clock cycle whenLOADis HIGH.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.