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Codiode/Problems/Sequential Logic

PISO: Programmable Start Position

HardLogic CircuitBuild

Communication protocols often require transmitting variable-length data words or selectively sending the upper bits of a register. A programmable start position parallel-in serial-out (PISO) shift register enables this exact partial-word transmission.

On the clock cycle where load is 1, the circuit captures the 8-bit data D and the 3-bit index START. The output Q_serial outputs the bit at index START of the loaded data. On subsequent cycles where load is 0, the circuit shifts out the remaining bits in descending order. Once D[0] is transmitted, Q_serial outputs 0 on all subsequent cycles until a new load occurs.

| Cycle | load | START | Q_serial | |-------|--------|---------|------------| | 0 | 1 | 4 | D[4] | | 1 | 0 | X | D[3] | | 2 | 0 | X | D[2] | | 3 | 0 | X | D[1] | | 4 | 0 | X | D[0] | | 5 | 0 | X | 0 |

Constraints

  • Implement synchronous logic triggered on the rising edge of the clock.
  • Use an 8:1 MUX to dynamically select the output bit based on the current shift position.
  • Output 0 when all bits from the start position down to 0 have been shifted out.

Topics

MultiplexersState MachinesShift Registers

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