PISO: Parallel Load Before Shift Complete Debug
An auto-loading 4-bit Parallel-In Serial-Out (PISO) shift register converts continuous parallel data into a serial bitstream.
Expected behavior:
When Enable is 1, the circuit automatically loads the parallel inputs D[3:0] and shifts them out over 4 clock cycles. The internal load signal must assert exactly once every 4 cycles (cycles 1, 5, 9, etc.) to capture new data without interrupting the current shift sequence.
Simulation shows that the serial output truncates the first word. When providing continuous Enable=1 with a first word of 1010 and a second word of 1100, the output Q_serial shows 1, 0, 1, 1, 0, 0. The internal load signal is asserting prematurely at cycle 3 instead of cycle 5. This timing protocol violation overwrites the remaining bits of the first word.
Inspect the internal load counter and correct the fault.
Constraints
- Do not modify the top-level input or output ports.
- The circuit must correctly output all 4 bits of each word before loading the next word.
Topics
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