PISO with Tristate Output Enable
Multiple chips on a single serial bus will cause contention if all drive the line simultaneously. Tristate output buffers allow multiple shift registers to share a single serial data line by disconnecting inactive chips.
Construct a 4-bit Parallel-In Serial-Out (PISO) shift register. On every clock cycle, the internal 4-bit register updates based on the load signal. When load is 1, the register loads the parallel inputs: D0 into Q0, D1 into Q1, D2 into Q2, and D3 into Q3. When load is 0, the register shifts right: sin moves into Q0, Q0 into Q1, Q1 into Q2, and Q2 into Q3.
The OE_bar signal controls bus access for the final stage Q3:
| OE_bar | sout | |----------|--------| | 0 | Q3 | | 1 | Z |
Constraints
- Use exactly four D flip-flops for the internal register.
- Implement a tristate buffer for the
soutpin. - The internal shift register must continue to load and shift data on every clock cycle even when
OE_baris 1.
Topics
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