PISO: Back-to-Back Loading Without Gaps
A positive-edge-triggered 4-bit Parallel-In Serial-Out (PISO) shift register captures the parallel data D[3:0] when LOAD is HIGH, and shifts the bits left to output the MSB to SOUT when LOAD is LOW.
Six input signals are provided: CLK (clock, period 2), LOAD (control input), and D3 through D0 (parallel data inputs).
Trace the serial output SOUT across all 16 time steps.
Constraints
- The shift register state and output only transition on the LOW-to-HIGH edge of
CLK. - The output
SOUTalways reflects the current value of the most significant bit (MSB) of the internal register. - Assume the initial state of the shift register is all zeros.
Topics
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