PISO: LOAD Pulse Width Requirement
A positive-edge-triggered 4-bit Parallel-In Serial-Out (PISO) shift register captures a hardwired parallel input of 1101 (D3=1, D2=1, D1=0, D0=1) when LOAD is HIGH at the rising edge of CLK. When LOAD is LOW at the rising edge, the register shifts its contents right (from D3 toward D0), shifting in a 0 at the MSB, and updating SOUT with the new D0 value.
Three signals are shown: CLK (clock, period 2), LOAD (synchronous load control) and SOUT (serial output, initially 0).
Trace SOUT across all 16 time steps.
Constraints
- The internal register is 4 bits wide and initialized to 0000.
- The serial input (shifted into D3 during a shift operation) is permanently tied to 0.
Topics
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