8-Bit PISO: MSB-First Serial Output
Standard SPI peripherals require data transmission to begin with the most significant bit. A parallel-in serial-out shift register converts internal byte-wide data into a single-wire bitstream formatted for these sensors.
When load is 1, the circuit captures the 8-bit input D on the rising edge of the clock. When load is 0, the register shifts its contents on each rising edge, outputting the bits sequentially on sout. The transmission must be MSB-first: D[7] appears on sout immediately after the load cycle, followed by D[6] through D[0] on subsequent clock cycles.
| load | Action | sout (after clock edge) | |--------|--------|---------------------------| | 1 | Load | D[7] | | 0 | Shift | D[6], then D[5], etc. |
Constraints
- Synchronous logic only: all state elements must share the same clock.
- The serial output
soutmust be driven directly by the final flip-flop in the shift chain. - Do not reverse the bit order externally: the shift chain itself must be wired to shift from MSB to LSB.
Topics
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