4-Bit PISO: Load and Shift Waveform
A positive-edge-triggered 4-bit Parallel-In Serial-Out (PISO) shift register loads parallel data when LOAD is HIGH and shifts data when LOAD is LOW. The parallel inputs are hardwired to 1011 (D3=1, D2=0, D1=1, D0=1) and the serial input is hardwired to 0. Three signals are shown: CLK (clock, period 2), LOAD (control input) and Q_serial (output of the last stage Q3, initially 0). Trace Q_serial across all 12 time steps.
Constraints
- The shift register is strictly positive-edge-triggered.
- During a shift operation (
LOAD=0), data moves in the following direction: Serial Input →Q0→Q1→Q2→Q3. Q_serialis directly connected to the output ofQ3.
Topics
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