4-Bit PISO: MUX-at-D Construction
Parallel-in, serial-out (PISO) registers convert internal wide data buses into single-bit streams for UARTs, SPI interfaces, and network serializers. The standard synchronous approach uses a 2:1 multiplexer at the input of every flip-flop to select between loading new data and shifting existing data.
Construct a 4-bit PISO shift register. The circuit must capture a 4-bit parallel input synchronously and shift it out bit-by-bit.
| LOAD | Mode | D input to flip-flop i | |--------|------|----------------------------| | 1 | Load | Parallel input D[i] | | 0 | Shift| Output of stage Q[i-1] |
When LOAD is 1, the flip-flops capture D0, D1, D2, and D3 on the rising edge of CLK. When LOAD is 0, data shifts rightward from Q0 to Q3 on each rising edge of CLK. The shift-in value for the first stage (Q0) must be a constant 0. The serial output of the entire circuit is read from the final stage, Q3.
Constraints
- Use exactly four D flip-flops and four 2:1 multiplexers.
- All flip-flops must share the same
CLKsignal. - Implement a strictly synchronous load. Do not use asynchronous preset or clear pins.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.