SIPO: Variable-Length Frame Reception
Serial protocols like SPI and various sensor interfaces use programmable word lengths to support 8-bit, 12-bit, or 16-bit transfers dynamically. A variable-length Serial-In Parallel-Out (SIPO) shift register captures incoming bits and asserts a strobe signal only when the complete data frame is assembled.
The circuit continuously shifts the 1-bit din into the least significant bit of the 8-bit dout register on every rising edge of clk. A 3-bit input FRAME_LEN specifies the frame size minus one. For example, FRAME_LEN = 3 configures a 4-bit frame, and FRAME_LEN = 7 configures an 8-bit frame.
An internal counter must track the number of received bits. When the counter reaches FRAME_LEN, it must reset to 0 on the next clock cycle and assert the 1-bit STROBE output to 1. On all other cycles, the counter increments by 1 and STROBE remains 0. The 1-bit rst is a synchronous active-high reset that clears dout, STROBE, and the internal counter to 0.
Constraints
- Use a synchronous active-high reset for all registers.
- Register the
STROBEoutput to prevent combinational glitches. - Shift
dinintodout[0]and shift existing bits left towarddout[7]. - Shift
doutcontinuously on every clock cycle regardless of the counter state.
Topics
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