PISO: Stuck at D3 Every Cycle Debug
A 4-bit Parallel-In Serial-Out (PISO) shift register captures a parallel data word and transmits it sequentially over a single output.
Expected behavior:
When the LOAD input is 1, the 4-bit input D[3:0] is synchronously loaded into the internal flip-flops. When LOAD is 0, the data shifts left on each rising clock edge, outputting D3, then D2, then D1, and finally D0 on the Q_serial pin.
Simulation reveals a timing failure. The test sequence pulses LOAD high for one clock cycle to capture D = 1010 (where D3 = 1), then drives LOAD low for four cycles to shift the data out. Instead of the expected sequence 1, 0, 1, 0, the Q_serial output remains stuck at 1 for all subsequent cycles. The register continuously outputs the MSB and never shifts the remaining bits. Inspect the circuit and correct the fault.
Constraints
- The circuit must use exactly four D flip-flops.
- Do not add external logic gates outside the shift register data path.
- The shift direction is MSB first (left shift).
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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