Reconvergence of Synchronized Signals
Independent synchronizers resolving metastable states on different clock cycles destroy the timing relationship of related signals. Two asynchronous inputs, A_IN and B_IN, transition HIGH exactly on the rising edge of CLK at step 3. This causes the first-stage flip-flops of both independent two-stage synchronizers to go metastable. Assume the first stage of the A synchronizer resolves HIGH before the next rising edge, while the first stage of the B synchronizer resolves LOW and captures the HIGH state one cycle later.
Six signals are shown: CLK (clock, period 2), A_IN and B_IN (asynchronous inputs), A_SYNC and B_SYNC (synchronized outputs, initially 0), and ERROR (combinational output of A_SYNC XOR B_SYNC, initially 0). Each synchronizer consists of two positive-edge-triggered D flip-flops that update immediately on the rising edge of CLK.
Trace A_SYNC, B_SYNC, and ERROR across all 14 time steps.
Constraints
- Output updates for the sequential elements occur immediately on the rising edge of the clock.
- The
ERRORsignal is purely combinational and evaluatesA_SYNC XOR B_SYNCat every time step without delay.
Topics
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