Shift Register vs Synchronizer
A sequence of two D flip-flops acts as a pipeline delay for synchronous signals, but serves as a synchronizer for asynchronous signals by isolating metastability. A positive-edge-triggered flip-flop captures its input on the LOW-to-HIGH transition of CLK. If an input transitions exactly on the clock edge, the capturing flip-flop's output becomes indeterminate (X) for that entire clock cycle.
Five signals are shown: CLK (clock, period 2), D_SYNC (synchronous input), D_ASYNC (asynchronous input), Q_S2 (second-stage output of the synchronous pipeline, initially 0), and Q_A1 (first-stage output of the synchronizer, initially 0).
Trace Q_S2 and Q_A1 across all 10 time steps. Use X for any indeterminate states.
Constraints
- Evaluate all flip-flop captures strictly at the LOW-to-HIGH clock transitions.
- A signal must be stable during the clock edge to be captured deterministically.
Q_S2is driven by the internal first-stage output of the synchronous pipeline.
Topics
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