Glitch Filter for Asynchronous Inputs
Mechanical switches bounce and electromagnetic interference causes nanosecond spikes on external pins. A glitch filter rejects this transient noise by requiring the signal to hold a steady value before propagating into the synchronous domain.
The circuit must monitor the asynchronous input din on every rising edge of clk. The output dout must only update to the value of din if din has been sampled at that new value for three consecutive clock cycles. If din fluctuates before three cycles have elapsed, dout retains its previous state. Upon active-high rst, dout and all internal states must clear to 0.
| din history (last 3 cycles) | dout (current) | dout (next) | |-------------------------------|------------------|---------------| | 1, 1, 1 | 0 | 1 | | 1, 1, 1 | 1 | 1 | | 0, 0, 0 | 1 | 0 | | 0, 0, 0 | 0 | 0 | | Any other mix | 0 | 0 | | Any other mix | 1 | 1 |
Constraints
- Use only D flip-flops and basic logic gates.
- Trigger all sequential elements on the rising edge of
clk. - Reset all state elements synchronously using
rst.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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