Registered Output Causing Late Response
An AXI stream receiver must immediately deassert its ready signal when the internal FIFO asserts full to prevent data overrun.
Expected behavior:
| full | ready | |--------|---------| | 0 | 1 | | 1 | 0 |
Simulation shows ready = 1 during the exact cycle that full transitions from 0 to 1. The ready signal drops a cycle late, causing the receiver to accidentally accept an extra word of data. Inspect the circuit and correct the fault.
Constraints
- Do not add additional input or output ports.
- The
readysignal must respond combinationally to thefullsignal. - Use only standard logic gates and remove any sequential elements on the output path.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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