Reset Synchronizer Driven by Wrong Clock
A multi-clock system requires synchronized resets to ensure safe recovery times across all domains.
Expected behavior: The circuit receives a global asynchronous active-low reset rst_n. It must generate three synchronized active-low resets: rst_sync_a, rst_sync_b, and rst_sync_c. Each synchronized reset must assert asynchronously the moment rst_n goes low. Each synchronized reset must deassert synchronously after two rising edges of its respective clock domain: clk_a, clk_b, and clk_c.
Simulation reports recovery time violations in domains B and C during the reset deassertion phase. Inspection of the waveforms shows rst_sync_b and rst_sync_c deasserting synchronously with clk_a instead of their respective clocks.
Inspect the circuit and correct the fault.
Constraints
- The circuit must assert all synchronized resets asynchronously.
- The circuit must use a standard two-stage flip-flop synchronizer for each clock domain.
- Do not modify the existing input and output ports.
Topics
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