Ring Counter: 0000 Permanent Lockup Debug
A 4-bit ring counter circulates a single active high bit through four flip-flops to generate sequential timing signals.
Expected behavior:
| Clock Edge | Q3 | Q2 | Q1 | Q0 | |--------------|------|------|------|------| | 1 | 1 | 0 | 0 | 0 | | 2 | 0 | 1 | 0 | 0 | | 3 | 0 | 0 | 1 | 0 | | 4 | 0 | 0 | 0 | 1 | | 5 | 1 | 0 | 0 | 0 |
Simulation shows Q3=0, Q2=0, Q1=0, and Q0=0 for 10 consecutive clock cycles after power-on. The outputs remain permanently zero.
Inspect the circuit and correct the fault.
Constraints
- The counter must self-correct from the all-zeros state within one clock cycle
- Do not change the total number of flip-flops
- Only basic logic gates may be added to the feedback path
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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