Ring Counter: One-Hot Outputs as Decoder Replacement
Time-critical control units often use one-hot state machines to eliminate decode logic delays. A ring counter generates a one-hot sequence natively by passing a single high bit through a circular shift register. A standard binary counter requires an external decoder to produce the same N distinct control signals.
The ring counter uses N flip-flops and zero decode gates. The binary counter uses ceil(log2(N)) flip-flops and a decoder consisting of N AND gates, each with ceil(log2(N)) inputs.
Compare the hardware cost of both approaches for different sequence lengths. Determine the crossover point where the decoder logic outweighs the cost of additional flip-flops.
Constraints
- Assume standard D flip-flops (
DFF) are used for all registers. - Assume the decoder is implemented using single-stage AND gates.
- Area cost is measured by counting flip-flops and total combinational gate inputs.
Topics
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