Ring Counter: Q3 Stuck-at-1 Fault Trace
A 4-bit ring counter circulates a single active-high bit to sequence control signals in digital state machines.
Expected behavior:
| Clock Cycle | Q3 | Q2 | Q1 | Q0 | |-------------|------|------|------|------| | 0 (Reset) | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | | 2 | 0 | 0 | 1 | 0 | | 3 | 0 | 0 | 0 | 1 | | 4 | 1 | 0 | 0 | 0 |
Simulation shows the counter initializing correctly to 1000 at reset. After the first clock cycle, the output transitions to 1100 instead of the expected 0100. After the second clock cycle, the output becomes 1110. A growing multi-hot state appears because the circuit is circulating an additional permanent high bit. Inspect the circuit and correct the fault.
Constraints
- Do not alter the clock or reset distribution networks.
- Maintain the existing 4-bit shift register architecture.
- The circuit must strictly produce one-hot states after initialization.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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