Ring Counter Time-Slot Multiplexer
Time-division multiplexing systems assign distinct time slots to multiple data streams over a single communication channel. A standard binary counter requires a 2-to-4 decoder to separate these channels. Using a ring counter for channel selection provides one-hot decoded outputs natively, generating mutually exclusive enable signals directly and eliminating the need for additional combinational logic.
Implement a 4-bit ring counter that directly controls a 4-to-1 multiplexer. On an active-high rst signal, the counter must initialize to Q0 = 1 with all other state bits at 0. On each rising edge of clk, the high bit shifts to the next position in a circular sequence. The output Y must route the input data line D corresponding to the currently active Q signal.
| Q3 | Q2 | Q1 | Q0 | Y | |------|------|------|------|-----| | 0 | 0 | 0 | 1 | D0| | 0 | 0 | 1 | 0 | D1| | 0 | 1 | 0 | 0 | D2| | 1 | 0 | 0 | 0 | D3|
Constraints
- Use exactly four D flip-flops for the state machine.
- Connect the flip-flop outputs directly to the multiplexer data path logic.
- Do not use a binary counter or binary-to-decimal decoder.
- Reset must be asynchronous and active-high.
Topics
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