Ripple Counter with Asynchronous CLEAR
Real-world hardware requires a reliable method to reset to a known state on power-up or during a system fault without waiting for the next clock edge. A 4-bit ripple counter with an asynchronous clear achieves this by instantly driving all state bits to zero the moment the reset line is asserted.
Construct a 4-bit up-counter using cascaded flip-flops. The counter increments its 4-bit output Q on every falling edge of CLK. When the active-low CLR_bar input is driven to 0, all bits of Q must become 0 immediately, completely independent of the CLK state. When CLR_bar is 1, the counter resumes normal operation.
| CLR_bar | CLK | Q (current) | Q (next) | |-----------|-------|---------------|------------| | 0 | X | X | 0 | | 1 | ↓ | N | N + 1 | | 1 | 1/0/↑ | N | N |
Constraints
- Use exactly four flip-flops configured to toggle.
- Connect the
CLR_barinput to the asynchronous clear port of every flip-flop simultaneously. - Do not use synchronous reset logic in the data path.
- Output
Qmust be a 4-bit bus.
Topics
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