Sequential Logic Race Condition
A two-stage register pipeline delays an input signal by two clock cycles to align data paths.
Expected behavior:
| clk edge | In | Out | |------------|------|-------| | Initial | 0 | 0 | | 1 | 1 | 0 | | 2 | 0 | 1 | | 3 | 1 | 0 | | 4 | 0 | 1 |
Simulation shows Out = 1 immediately after clock edge 1 when In = 1. The pipeline exhibits a one-cycle latency instead of the expected two-cycle latency. Inspect the circuit and correct the fault.
Constraints
- Do not change the module interface or port names.
- The design must maintain a true two-cycle structural delay.
- Registers must trigger on the positive edge of
clk.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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