Serial Link: Framing Error Detection
A UART receiver validates incoming 10-bit frames (1 start bit, 8 data bits, 1 stop bit) by checking if the 10th bit is a logic 1.
Four signals are shown: CLK (clock, positive-edge-triggered, period 2), RX (serial input, idles HIGH), DATA_VALID (output, initially 0), and FRAMING_ERROR (output, initially 0).
Trace DATA_VALID and FRAMING_ERROR across all 46 time steps for two consecutive frames.
Constraints
- The receiver evaluates the stop bit on the 10th rising edge of
CLKafter (and including) the start bit detection. - If the stop bit is 1,
DATA_VALIDis asserted HIGH for exactly one clock cycle. - If the stop bit is 0, the frame is discarded and
FRAMING_ERRORis asserted HIGH for exactly one clock cycle. - Back-to-back frames are supported: a new start bit can occur immediately on the clock cycle following a stop bit.
Topics
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