Serial Shift Register: Bit-Banging Pattern Generator

HardLogic CircuitBuild

Protocol simulators and self-test circuits often require continuous periodic waveforms generated without microcontrollers or lookup tables. A recirculating shift register acts as a bit-banged pattern generator by continuously looping a hardcoded sequence in hardware.

Implement an 8-bit recirculating shift register that outputs a repeating 10110100 pattern.

When rst is 1, the register synchronously clears to 00000000.
When rst is 0 and load is 1, the register synchronously loads the binary value 10110100.
When rst is 0 and load is 0, the register shifts its contents left by one position on each clock cycle.
The most significant bit drives the out port and simultaneously feeds back into the least significant bit.

Constraints

Use exactly one 8-bit state register.
Implement synchronous active-high reset and load signals.
Do not use external ROM or memory elements.
The parallel load must take priority over the shift operation.

Topics

Sequential LogicShift RegistersPattern Generator

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Serial Shift Register: Bit-Banging Pattern Generator

HardLogic CircuitBuild

Implement an 8-bit recirculating shift register that outputs a repeating 10110100 pattern.

When rst is 1, the register synchronously clears to 00000000.
When rst is 0 and load is 1, the register synchronously loads the binary value 10110100.
When rst is 0 and load is 0, the register shifts its contents left by one position on each clock cycle.
The most significant bit drives the out port and simultaneously feeds back into the least significant bit.

Constraints

Use exactly one 8-bit state register.
Implement synchronous active-high reset and load signals.
Do not use external ROM or memory elements.
The parallel load must take priority over the shift operation.

Topics

Sequential LogicShift RegistersPattern Generator

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Serial Shift Register: Bit-Banging Pattern Generator

Constraints

Topics

Solve this problem

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Serial Shift Register: Bit-Banging Pattern Generator

Constraints

Topics

Solve this problem

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