PISO: Parallel-to-Serial Conversion for SPI Transmission
Serial Peripheral Interface (SPI) master transmitters rely on parallel-to-serial conversion to serialize byte-wide data onto a single wire. This 8-bit PISO handles the core transmission phase of an SPI transaction.
The circuit operates on a continuous clock and receives an 8-bit parallel input D and an active-low chip select CS_bar. When CS_bar transitions from 1 to 0, the circuit must synchronously generate an internal LOAD pulse for exactly one clock cycle. During this cycle, the 8-bit value D is captured into an internal shift register.
On the clock cycle immediately following the LOAD pulse, the most significant bit (D[7]) must appear on the serial output tx. For the next 7 clock cycles, the remaining bits (D[6] down to D[0]) are shifted out to tx. When CS_bar is 1, tx must output 0.
Constraints
- Implement an 8-bit shift register using D flip-flops.
- Use a synchronous edge detector to generate the internal
LOADsignal fromCS_bar. - Output 0 on
txwheneverCS_baris 1 or during theLOADcycle. - Shift out the most significant bit first.
Topics
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