Serial Transmitter with Output Enable for Bus Sharing
Multi-master serial buses like SPI share a single data line across multiple devices. To prevent bus contention that corrupts data and damages drivers, inactive transmitters must disconnect their outputs from the shared bus using tristate logic.
Construct a shared serial transmission block containing two 8-bit Parallel-In Serial-Out (PISO) shift registers. The registers share a single 1-bit output Y.
When the 1-bit load signal is 1, PISO 0 loads the 8-bit input D0 and PISO 1 loads the 8-bit input D1. When load is 0, both registers shift their data out internally on every clock cycle, MSB (bit 7) first.
The active-low 1-bit chip select pins CS0_bar and CS1_bar control the output buffers. Only one chip select will be low at a time.
| CS0_bar | CS1_bar | Y | |-----------|-----------|-----| | 0 | 1 | PISO 0 current bit | | 1 | 0 | PISO 1 current bit | | 1 | 1 | Z (High Impedance) |
Constraints
- Use tristate buffers for the output
Y. - Shift data out MSB (bit 7) first.
- Both shift registers must shift continuously when
loadis 0, regardless of their chip select state. - Do not drive
Yto 0 or 1 when both chip selects are high.
Topics
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