Serial Data with One Corrupted Bit: Error Detection Limit
A serial link monitor uses an XOR gate to detect bit-level mismatches between expected and received data, and a positive-edge-triggered sticky flip-flop to latch any detected error.
Five signals are shown: CLK (clock, period 2), TX_DATA (expected transmitted byte), RX_DATA (actual received byte), ERR_BIT (combinational mismatch flag), and ERR_LATCH (sticky error state, initially 0).
Trace ERR_BIT and ERR_LATCH across all 16 time steps.
Constraints
ERR_BITis a purely combinational output that continuously evaluatesTX_DATAXORRX_DATA.ERR_LATCHcaptures the logical OR of its current state andERR_BITon every LOW-to-HIGH transition ofCLK.- Changes to data inputs between clock edges immediately affect combinational outputs but do not affect sequential state until the next rising clock edge.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.