Shift Register Based Fall Through FIFO
High-speed communication interfaces require buffering where traditional pointer-based tracking introduces critical path delays. A fall-through bubble FIFO solves this by allowing incoming data to automatically ripple down to the lowest available empty slot using localized valid bits instead of centralized read and write pointers.
Construct a 2-stage, 1-bit wide synchronous fall-through FIFO. The circuit consists of Stage 1 (top) and Stage 0 (bottom). Each stage maintains a 1-bit data register and a 1-bit valid register (v1 and v0).
State transition rules evaluated on the rising edge of clk: * If rst is 1: clear v1 and v0. * If push is 1 and full is 0: load din into Stage 1 and set v1 to 1. * If v1 is 1, and either v0 is 0 or pop is 1: move Stage 1 data to Stage 0, set v0 to 1, and clear v1 (unless a new push simultaneously loads Stage 1). * If pop is 1 and no data is moving from Stage 1: clear v0. * If full is 1, new push requests are ignored.
Output assignments: * empty: 1 when both v1 and v0 are 0. * full: 1 when both v1 and v0 are 1. * dout: continuous assignment to the Stage 0 data register.
Constraints
- Use only D flip-flops and combinational logic gates.
- Do not use RAM or memory blocks.
- Implement exactly 2 stages of depth.
- Drive outputs
empty,full, anddoutcombinationally based on the current register states.
Topics
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