Shift Register Pipeline Collapse
A 3-stage shift register pipeline delays an input signal by three clock cycles to synchronize data across stages.
Expected behavior:
When Din changes, Dout must reflect that change exactly three rising clock edges later.
Simulation shows Dout = 1 immediately on the first rising edge of Clk when Din = 1 is applied. The pipeline collapses and data propagates through all three stages in a single clock cycle. Inspect the circuit and correct the fault.
Constraints
- Do not change the module interface ports.
- The circuit must use exactly three flip-flops.
- The output must rely on the sequential clock edges, not combinational bypasses.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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