Divide-by-2 Clock Generator
Clock trees in every SoC derive slower domains from a master oscillator. The atomic even divider is a register whose data input is its own inverted output: each rising edge of clk flips the stored bit, so div_clk runs at exactly half the input frequency.
On every rising edge of clk with rst low, div_clk toggles. While rst is high, div_clk is forced to 0.
| rst | div_clk (current) | div_clk (next) | |-------|----------------------|--------------------| | 1 | x | 0 | | 0 | 0 | 1 | | 0 | 1 | 0 |
Constraints
- Use exactly one resettable register (REG) and one inverter (NOT).
- The register must clock on the rising edge of
clk. - Route the inverted output back to the register data input to create the toggle.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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